Serializer/deserializer (“SERDES”) devices are frequently used in high-speed communication networks in which an interface must be provided between parallel bus-connected devices and high-speed serial communication networks, such as those implemented through optical fiber interconnections. Individual channels of multichannel SERDES devices are currently tested separately using an on-chip serial feedback, or wired on-the-board serial feedback. Current testing techniques require separate testing of each channel of a SERDES device and do not allow for the simultaneous testing of multiple channels using one source of data.
For example, U.S. Published Application No. 2003/0023912, entitled “Integrated Testing of Serializer/Deserializer in FPGA”, describes a field programmable gate array (FPGA) device that includes a high-speed serializer/deserializer (SERDES). The configurable logic blocks (CLBs) of the FPGA are initially configured to test the SERDES by stimulating the SERDES with high-speed pattern generation and optional CRC checks. The test is evaluated by a bit error rate tester and the results are stored for later access. Test results are accessible by external test equipment. The elements of the FPGA used for testing are then reprogrammed for proper device operation. In the system described, each SERDES channel is individually tested, with the testing logic duplicated for each channel.
In U.S. Published Application No. 2003/0031133, entitled “Line Loop Back for Very High Speed Application”, a test methodology for high-speed SERDES devices is described in which externally generated parallel data are applied through a network of buffers and multiplexers to the input stage of a serializer, the communications link is looped back so that the high-speed serial data traverses the serial transmission channel in both directions and is deserialized and presented to external analysis circuitry through low-speed logic. Each SERDES channel, however, is tested on a one-by-one basis, with duplication of the specialized low-speed logic for each path being tested.
Accordingly, a need arises for an apparatus, system and method that easily and efficiently permits testing of all channels of SERDES devices, simultaneously and at full or lower speed, without a need to duplicate test equipment or laboriously reconfigure the device for normal operation following testing.